DocumentCode
2480200
Title
Efficient encoding for a family of quasi-cyclic LDPC codes
Author
Hocevar, Dale E.
Author_Institution
DSP Solutions R&D Center, Texas Instruments, Dallas, TX, USA
Volume
7
fYear
2003
fDate
1-5 Dec. 2003
Firstpage
3996
Abstract
In general, encoding for LDPC codes can be difficult to realize efficiently. The paper presents techniques and architectures for LDPC encoding that are efficient and practical for a particular class of codes. These codes are the irregular partitioned permutation LDPC codes recently introduced by the author (Hocevar, D.E., Proc. IEEE Int. Conf. on Commun., p.2708-12, 2003). Since these codes are quasi-cyclic, it is known that a simpler encoding process does exist. The paper goes beyond that basic method by exploiting other structural properties to allow for a simpler and faster encoding process, in both software and hardware. Solutions for some rank deficient codes are also given.
Keywords
matrix algebra; parity check codes; encoding process; irregular partitioned permutation LDPC codes; parity check matrices; quasi-cyclic codes; rank deficient codes; Computer architecture; Digital signal processing; Encoding; Hardware; Instruments; Iterative decoding; Parity check codes; Research and development; Shift registers; Sparse matrices;
fLanguage
English
Publisher
ieee
Conference_Titel
Global Telecommunications Conference, 2003. GLOBECOM '03. IEEE
Print_ISBN
0-7803-7974-8
Type
conf
DOI
10.1109/GLOCOM.2003.1258979
Filename
1258979
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