A mini-SiPM array for PET detectors implemented in 0.35-µm HV CMOS technology

Author

Braga, Leo H C ; Pancheri, Lucio ; Gasparini, Leonardo ; Henderson, Robert K. ; Stoppa, David

Author_Institution

Fondazione Bruno Kessler (FBK), Trento, Italy

fYear

2011

fDate

3-7 July 2011

Firstpage

181

Lastpage

184

Abstract

A new architecture for Positron Emission Tomography visible-light detectors is presented. The architecture is based on mini-SiPMs (arrays of 32 SPADs), which are locally digitized. With this architecture we expect to achieve a high fill factor while still performing an early enough analog-to-digital conversion so as to avoid interconnect parasitics common of standard SiPMs. The detector is implemented as a 14 × 10 pixel array where each pixel contains a mini-SiPM, a digital counter and individual SPAD SRAMs for disabling high DCR devices. The achieved fill factor is 29% and the expected maximum event rate is 16 kcps.

Keywords

CMOS integrated circuits; SRAM chips; analogue-digital conversion; avalanche photodiodes; elemental semiconductors; integrated optoelectronics; optical arrays; photodetectors; photomultipliers; positron emission tomography; silicon; DCR devices; HV CMOS technology; PET detectors; SPAD; SPAD SRAM; Si; analog-to-digital conversion; digital counter; miniSiPM array; pixel array; positron emission tomography visible-light detectors; silicon photomultiplier; size 0.35 mum; Arrays; CMOS integrated circuits; Detectors; Photonics; Pixel; Positron emission tomography; Timing; HV CMOS; PET; SPAD; SiPM; digital SiPM; mini-SiPM;

fLanguage

English

Publisher

ieee

Conference_Titel

Ph.D. Research in Microelectronics and Electronics (PRIME), 2011 7th Conference on

Conference_Location

Trento

Print_ISBN

978-1-4244-9138-4

Electronic_ISBN

978-1-4244-9136-0

Type

conf

DOI

10.1109/PRIME.2011.5966247

Filename

5966247