• DocumentCode
    2480426
  • Title

    Maximizing crosstalk-induced slowdown during path delay test

  • Author

    Gope, Dibakar ; Walker, D.M.H.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA
  • fYear
    2012
  • fDate
    Sept. 30 2012-Oct. 3 2012
  • Firstpage
    159
  • Lastpage
    166
  • Abstract
    In this paper, we present a timing-driven test generator to sensitize multiple aligned aggressors coupled to a delay-sensitive victim path to detect the combination of a delay spot defect and crosstalk-induced slowdown. The framework uses parasitic capacitance information, timing windows and crosstalk-induced delay estimates to screen out unaligned or ineffective aggressors coupled to a victim path, speeding up crosstalk pattern generation. In order to induce maximum crosstalk slowdown along a path, aggressors are prioritized based on their potential delay increase and timing alignment. The test generation engine introduces the concept of alignment-driven path sensitization to generate paths from inputs to coupled aggressor nets that meet timing alignment and direction requirements. In addition, two new crosstalk-driven dynamic test compaction algorithms are developed to control the increase in test pattern count. The proposed test generation algorithm is applied to ISCAS85 and ISCAS89 benchmark circuits. SPICE simulation results demonstrate the ability of the alignment-driven test generator to increase crosstalk-induced delays along victim paths.
  • Keywords
    SPICE; automatic test pattern generation; circuit testing; crosstalk; delays; timing; ISCAS85 benchmark circuit; ISCAS89 benchmark circuit; SPICE simulation; alignment-driven path sensitization; crosstalk pattern generation; crosstalk-driven dynamic test compaction algorithm; crosstalk-induced delay estimate; crosstalk-induced slowdown maximization; delay spot defect; delay-sensitive victim path; direction requirement; ineffective aggressors; maximum crosstalk slowdown; multiple aligned aggressor sensitization; parasitic capacitance information; path delay test; potential delay; test generation algorithm; test generation engine; test pattern count; timing alignment requirement; timing window; timing-driven test generator; unaligned aggressors; Automatic test pattern generation; Compaction; Couplings; Crosstalk; Delay; Logic gates; Automatic test pattern generation (ATPG); aggressors; crosstalk; path delay test;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design (ICCD), 2012 IEEE 30th International Conference on
  • Conference_Location
    Montreal, QC
  • ISSN
    1063-6404
  • Print_ISBN
    978-1-4673-3051-0
  • Type

    conf

  • DOI
    10.1109/ICCD.2012.6378635
  • Filename
    6378635