DocumentCode
2480681
Title
WaveSync: A low-latency source synchronous bypass network-on-chip architecture
Author
Yang, Yoon Seok ; Kumar, Reeshav ; Choi, Gwan ; Gratz, Paul
Author_Institution
Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA
fYear
2012
fDate
Sept. 30 2012-Oct. 3 2012
Firstpage
241
Lastpage
248
Abstract
WaveSync is a low-latency focused, network-on-chip architecture for globally-asynchronous locally-synchronous (GALS) designs. WaveSync facilitates low-latency communication leveraging the source-synchronous clock sent with the data, to time components in the downstream routers data-path to reduce the number of synchronizations needed. WaveSync accomplishes this by partitioning the router components at each node into different clock-domains, each synchronized with one of the the orthogonal incoming source synchronous clocks in a GALS 2D mesh network. The data and clock subsequently propagate through each node/router, synchronously, until the destination is reached, regardless of the number of hops it may take. As long as the data travel in the path of clock propagation, and no congestion is encountered, it will be propagated without latching, as if in a long-combinatorial path, with both the clock and the data accruing delay at the same rate. The result is that the need for synchronization between the mesochronous nodes and/or the asynchronous control associated with typical GALS network is completely eliminated. The proposed WaveSync network outperforms conventional GALS networks by 87-90% in average nanosecond latency with 1.8-6.5 times more throughput across synthetic traffic patterns and SPLASH-2 benchmark suite.
Keywords
clocks; network routing; network-on-chip; synchronisation; GALS 2D mesh network; GALS designs; GALS network; SPLASH-2 benchmark suite; WaveSync network; asynchronous control; clock propagation; clock-domains; downstream router data-path; globally-asynchronous locally-synchronous designs; long-combinatorial path; low-latency communication; low-latency source synchronous bypass network-on-chip architecture; mesochronous nodes; source-synchronous clock; synchronization reduction; synthetic traffic patterns; time components; Bandwidth; Clocks; Control systems; Microarchitecture; Routing; Silicon compounds; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design (ICCD), 2012 IEEE 30th International Conference on
Conference_Location
Montreal, QC
ISSN
1063-6404
Print_ISBN
978-1-4673-3051-0
Type
conf
DOI
10.1109/ICCD.2012.6378647
Filename
6378647
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