Title :
Fast error aware model for arithmetic and logic circuits
Author :
Zaynoun, Samy ; Khairy, Muhammad S. ; Eltawil, Ahmed M. ; Kurdahi, Fadi J. ; Khajeh, Amin
Author_Institution :
Electr. Eng. & Comput. Sci. Dept., Univ. of California Irvine, Irvine, CA, USA
fDate :
Sept. 30 2012-Oct. 3 2012
Abstract :
As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing violations) within the block. Consequently, these failure models are then used to examine how circuit-level failures affect system-level reliability. A case study consisting of a CORDIC DSP unit employing the proposed model provides tradeoffs between power, performance and reliability.
Keywords :
delay estimation; digital arithmetic; digital signal processing chips; failure analysis; integrated circuit reliability; logic circuits; power aware computing; CORDIC DSP unit; arithmetic circuit; circuit level failure identification; digital block operation; dynamic voltage scaling; error aware model; error free margin; failure model; logic circuit; propagation delay estimation; system-level reliability; Delay; Integrated circuit modeling; Logic gates; Propagation delay; Table lookup; Vectors; error aware model; failure analysis; timing violation; voltage over sclaing;
Conference_Titel :
Computer Design (ICCD), 2012 IEEE 30th International Conference on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-3051-0
DOI :
10.1109/ICCD.2012.6378659
