Title :
Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications
Author :
Vezyrtzis, Christos ; Tsividis, Yannis ; Nowick, Steven M.
Author_Institution :
Dept. of Electr. Eng., Columbia Univ. in the City of New York, New York, NY, USA
fDate :
Sept. 30 2012-Oct. 3 2012
Abstract :
A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst-case input rate. However, due to their rigid structure, they have sub-optimal energy for low- and varying-rate input streams. We introduce a complete methodology for designing reconfigurable delay lines which dynamically adapt granularity to traffic, on-the-fly, without stalling or disturbing normal operation. These lines have two modes: coarse- and fine-grain. During sparser traffic, the system is reconfigured to coarse-grain mode, thereby reducing total energy, and it reverts to fine-grain mode during denser traffic. In each case, overall delay is preserved. This strategy is especially beneficial for applications where input traffic is highly varied. The particular focus of this paper is on one promising domain, continuous-time digital signal processors (CT DSP´s), a new class of processors targeting low-energy applications. The proposed system includes two lightweight asynchronous control blocks: a digital controller to continuously monitor input traffic, and a micropipeline to dynamically reconfigure the entire delay line. With a complete implementation in a 0.13 um IBM CMOS technology, post-layout simulations demonstrate an average overall dynamic power reduction up to 45.5% compared to a non-adaptive design, with only minimal area overhead. The design methodology is modular, supporting extensions to multiple configuration modes to provide even greater power reduction for a variety of input traffic. While results are presented for CT DSP´s, significant benefits are also expected in many other domains where delay lines are used.
Keywords :
CMOS integrated circuits; asynchronous circuits; continuous time systems; delay lines; digital control; digital signal processing chips; energy conservation; pipeline processing; power aware computing; CT DSP; IBM CMOS technology; calibrated delay line; coarse-grain mode; continuous-time digital signal processor; digital controller; digital system; dynamic power reduction; dynamically-adaptive granularity; granularity dynamic adaptation; input traffic continuous monitoring; lightweight asynchronous control block; low-energy application; low-rate input stream; micropipeline; nonadaptive design; pipelined delay line design; post-layout simulation; real-time pipeline; reconfigurable delay line design; rigid structure; static granularity; suboptimal energy; total energy reduction; variable input traffic; varying-rate input stream; worst-case input rate; Clocks; Delay; Delay lines; Digital signal processing; Monitoring; Protocols; Real-time systems;
Conference_Titel :
Computer Design (ICCD), 2012 IEEE 30th International Conference on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-3051-0
DOI :
10.1109/ICCD.2012.6378660