Title :
A NMOS bulk voltage trimming offset calibration technique for a 6-bit 5GS/s Flash ADC
Author :
Vassou, Ch ; Mountrichas, L. ; Siskos, S.
Author_Institution :
Phys. Dept., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece
Abstract :
In this work a new high-resolution offset cancellation technique based on bulk-voltage trimming is presented, which can be applied to Flash analog-to-digital converters (ADCs). The offset calibration is achieved by digitally adjusting the bulk voltages of the differential pairs of the preamplifier consisting of NMOS transistors in a triple well technology. Furthermore this technique minimizes the power consumption using only one power supply. A 6-bit, 5GS/s Flash ADC is implemented in 1.2V 90nm CMOS process. Using proposed calibration technique, an input-referred sigma offset of 0.09 LSB compared to 1.8 LSB without the calibration is achieved.
Keywords :
CMOS integrated circuits; MOSFET; analogue-digital conversion; calibration; preamplifiers; CMOS process; NMOS bulk voltage trimming offset calibration technique; NMOS transistors; bit rate 5 Gbit/s; bulk-voltage trimming; flash ADC; flash analog-to-digital converters; high-resolution offset cancellation technique; input-referred sigma offset; power consumption; preamplifier; size 90 nm; voltage 1.2 V; word length 6 bit; CMOS integrated circuits; Calibration; Power demand; Preamplifiers; Threshold voltage; Transistors; Bulk voltage trimming; Flash analog-to-digital converter (ADC); Offset calibration; high sampling rate converters;
Conference_Titel :
Instrumentation and Measurement Technology Conference (I2MTC), 2012 IEEE International
Conference_Location :
Graz
Print_ISBN :
978-1-4577-1773-4
DOI :
10.1109/I2MTC.2012.6229430
