A high speed configurable FPGA architecture for bilateral filtering

Author

Kutty, J.S.S. ; Boussaid, F. ; Amira, A.

Author_Institution

Sch. of Electr. & Comput. Eng., Univ. of Western Australia, Perth, WA, Australia

fYear

2014

fDate

27-30 Oct. 2014

Firstpage

1248

Lastpage

1252

Abstract

This paper presents a high speed configurable FPGA architecture for bilateral filtering. The proposed architecture is highly pipelined, parallel and fully configurable. It can achieve an operating frequency of 450 MHz and a throughput of one pixel value per clock cycle. This is almost three times faster than any reported FPGA architecture with such a throughput. Line Buffering was implemented using a novel BRAM architecture that ensures access to all pixels of the filter window in a single clock cycle. The proposed BRAM architecture also addresses the high speed and throughput requirements of convolution functions in image processing algorithms.

Keywords

field programmable gate arrays; image filtering; random-access storage; BRAM architecture; bilateral filtering; block random access memory; clock cycle; convolution function; field programmable gate array; filter window; frequency 450 MHz; high speed configurable FPGA architecture; image processing algorithm; line buffering; pipelined parallel architecture; pixel value; throughput; Clocks; Computer architecture; Field programmable gate arrays; Image processing; Kernel; Real-time systems; Throughput; Bilateral filter; Convolution; High speed FPGA; Image Processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing (ICIP), 2014 IEEE International Conference on

Conference_Location

Paris

Type

conf

DOI

10.1109/ICIP.2014.7025249

Filename

7025249