DocumentCode :
2481337
Title :
Adaptive Backpressure: Efficient buffer management for on-chip networks
Author :
Becker, Daniel U. ; Jiang, Nan ; Michelogiannakis, George ; Dally, William J.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
fYear :
2012
fDate :
Sept. 30 2012-Oct. 3 2012
Firstpage :
419
Lastpage :
426
Abstract :
This paper introduces Adaptive Backpressure, a novel scheme that improves the utilization of dynamically managed router input buffers by continuously adjusting the stiffness of the flow control feedback loop in response to observed traffic conditions. Through a simple extension to the router´s flow control mechanism, the proposed scheme heuristically limits the number of credits available to individual virtual channels based on estimated downstream congestion, aiming to minimize the amount of buffer space that is occupied unproductively. This leads to more efficient distribution of buffer space and improves isolation between multiple concurrently executing workloads with differing performance characteristics. Experimental results for a 64-node mesh network show that Adaptive Backpressure improves network stability, leading to an average 2.6× increase in throughput under heavy load across traffic patterns. In the presence of background traffic, the proposed scheme reduces zero-load latency by an average of 31%. Finally, it mitigates the performance degradation encountered when latency- and throughput-optimized execution cores contend for network resources in a heterogeneous chip multi-processor; across a set of PARSEC benchmarks, we observe an average reduction in execution time of 34%.
Keywords :
buffer storage; circuit feedback; circuit stability; minimisation; multiprocessing systems; network routing; network-on-chip; performance evaluation; 64-node mesh network; PARSEC benchmarks; adaptive backpressure; background traffic; buffer management; buffer space distribution; buffer space minimization; downstream congestion; dynamically managed router input buffer utilization; execution time reduction; flow control feedback loop; heterogeneous chip multiprocessor; latency-optimized execution cores; multiple concurrently executing workload isolation improvement; network resources; network stability; on-chip networks; performance characteristics; performance degradation mitigation; stiffness adjustment; throughput-optimized execution cores; traffic conditions; traffic patterns; virtual channels; zero-load latency reduction; Aerospace electronics; Delay; Registers; Resource management; Switches; System recovery; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2012 IEEE 30th International Conference on
Conference_Location :
Montreal, QC
ISSN :
1063-6404
Print_ISBN :
978-1-4673-3051-0
Type :
conf
DOI :
10.1109/ICCD.2012.6378673
Filename :
6378673
Link To Document :
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