A 3D stacked high performance scalable architecture for 3D Fourier Transform

This paper proposes and evaluates a novel high-performance systolic architecture for 3D Fourier Transform specially tailored for 3D stacking integration with Through Silicon Vias. Our cuboid-shaped systolic network of orthogonally connected processing elements makes use of the DFT algorithm to compute an N₁×N₂×N₃-point 3D-FT with an asymptotic time complexity of O(N₁+N₂+N₃) multiplications. When compared with state-of-the-art 3D-FFT implementation on the Anton machine, a physical synthesized implementation of our architecture on the same 90nm technology node achieves 7.73× and 5.88× speed improvement when computing 16×1 6×16 and 32×3 2×32 FT, respectively.