DocumentCode :
2481746
Title :
Post-layout OPE-predicted redundant wire insertion for clock skew minimization
Author :
Yan, Jin-Tai ; Chen, Zhi-Wei
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Chung-Hua Univ., Hsinchu, Taiwan
fYear :
2012
fDate :
Sept. 30 2012-Oct. 3 2012
Firstpage :
504
Lastpage :
505
Abstract :
Based on the equilibrium concept of inserting load in a physical balance, the insertion of redundant wires can be used to minimize the clock skew in an OPE-predicted clock tree. For five tested benchmarks, the experimental results show that our proposed algorithm only increases 2.8% of the total load on the average for the insertion of OPE-predicted redundant wires and decreases 30.85 ps of the clock skew on the average to obtain the near zero-skew result in reasonable CPU time.
Keywords :
benchmark testing; clocks; integrated circuit interconnections; integrated circuit layout; minimisation; proximity effect (lithography); redundancy; wires (electric); OPE-predicted clock tree; benchmark testing; clock skew minimization; near zero-skew result; optical proximity effects; post-layout OPE-predicted redundant wire insertion; Algorithm design and analysis; Benchmark testing; Capacitance; Clocks; Minimization; Routing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2012 IEEE 30th International Conference on
Conference_Location :
Montreal, QC
ISSN :
1063-6404
Print_ISBN :
978-1-4673-3051-0
Type :
conf
DOI :
10.1109/ICCD.2012.6378695
Filename :
6378695
Link To Document :
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