DocumentCode
2482695
Title
Root Locus Plots and Iterative Decoding
Author
Kellett, Christopher M.
Author_Institution
Hamilton Inst., Nat. Univ. of Ireland, Maynooth
fYear
2006
fDate
13-15 Dec. 2006
Firstpage
1888
Lastpage
1893
Abstract
A well known class of error correction codes called low-density parity-check (LDPC) codes have been the subject of a great deal of recent study in the coding community as a result of their ability to approach Shannon´s fundamental capacity limit. Crucial to the performance of these codes is the use of an iterative decoder. We describe LDPC codes and the decoding algorithm and make a connection between the fixed points of the decoding algorithm and the well-known root locus plot. Via two example LDPC codes, we describe the insights afforded by the root locus plot
Keywords
discrete time systems; error correction codes; information theory; iterative decoding; parity check codes; root loci; Shannon fundamental capacity limit; error correction codes; iterative decoding; low-density parity-check codes; root locus plots; Communication channels; Digital communication; Error correction codes; Iterative algorithms; Iterative decoding; Parity check codes; Redundancy; Sequences; USA Councils; Visualization;
fLanguage
English
Publisher
ieee
Conference_Titel
Decision and Control, 2006 45th IEEE Conference on
Conference_Location
San Diego, CA
Print_ISBN
1-4244-0171-2
Type
conf
DOI
10.1109/CDC.2006.376931
Filename
4177969
Link To Document