Limit cycle frequency jittering of an asynchronous sigma-delta modulator

Author

Matic, Tomislav ; Svedek, Tomislav ; Herceg, Marijan

Author_Institution

Fac. of Electr. Eng., Josip Juraj Strossmayer Univ. of Osijek, Osijek, Croatia

fYear

2009

fDate

7-9 Oct. 2009

Firstpage

198

Lastpage

201

Abstract

This paper presents limit cycle frequency jittering of a first order Asynchronous Sigma-Delta Modulator (ASDM) implemented with Schmitt trigger. Particular interest is placed on a jitter of a Schmitt trigger hysteresis voltage (hysteresis jitter). Hysteresis jitter has been modeled in MATLAB^Â® Simulink and the model simulation has been compared with measurements for first ordered ASDM. Both simulation and measurement show that ASDM model limit cycle frequency depends on the hysteresis jitter.

Keywords

asynchronous circuits; hysteresis; jitter; mathematics computing; sigma-delta modulation; trigger circuits; ASDM model; MATLAB; Schmitt trigger; Simulink; first order asynchronous sigma-delta modulator; hysteresis jitter; hysteresis voltage; limit cycle frequency jittering; model simulation; Delta-sigma modulation; Frequency; Hysteresis; Jitter; Limit-cycles; MATLAB; Mathematical model; Trigger circuits; Variable speed drives; Voltage; Asynchronous sigma-delta; Limit cycle frequency; jittering;

fLanguage

English

Publisher

ieee

Conference_Titel

Telecommunication in Modern Satellite, Cable, and Broadcasting Services, 2009. TELSIKS '09. 9th International Conference on

Conference_Location

Nis

Print_ISBN

978-1-4244-4382-6

Electronic_ISBN

978-1-4244-4383-3

Type

conf

DOI

10.1109/TELSKS.2009.5339427

Filename

5339427