Title :
Designing efficient sorting algorithms for manycore GPUs
Author :
Satish, Nadathur ; Harris, Mark ; Garland, Michael
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA
Abstract :
We describe the design of high-performance parallel radix sort and merge sort routines for manycore GPUs, taking advantage of the full programmability offered by CUDA. Our radix sort is the fastest GPU sort and our merge sort is the fastest comparison-based sort reported in the literature. Our radix sort is up to 4 times faster than the graphics-based GPUSort and greater than 2 times faster than other CUDA-based radix sorts. It is also 23% faster, on average, than even a very carefully optimized multicore CPU sorting routine. To achieve this performance, we carefully design our algorithms to expose substantial fine-grained parallelism and decompose the computation into independent tasks that perform minimal global communication. We exploit the high-speed onchip shared memory provided by NVIDIA´s GPU architecture and efficient data-parallel primitives, particularly parallel scan. While targeted at GPUs, these algorithms should also be well-suited for other manycore processors.
Keywords :
merging; parallel algorithms; parallel architectures; shared memory systems; sorting; CUDA-based radix sorts; GPU architecture; comparison-based sort; fine-grained parallelism; high-performance parallel merge sort routines; high-performance parallel radix sort routines; high-speed onchip shared memory; manycore GPU; multicore CPU sorting routine; sorting algorithms; Algorithm design and analysis; Computer architecture; Concurrent computing; Data structures; Database systems; Global communication; Multicore processing; Parallel architectures; Parallel processing; Sorting;
Conference_Titel :
Parallel & Distributed Processing, 2009. IPDPS 2009. IEEE International Symposium on
Conference_Location :
Rome
Print_ISBN :
978-1-4244-3751-1
Electronic_ISBN :
1530-2075
DOI :
10.1109/IPDPS.2009.5161005