Reconfigurable FFT Design for Low Power OFDM Communication Systems

The FFT processor is the most speed critical part in the multi-carrier orthogonal frequency division multiplexing (OFDM) communication system. In these systems, low power is usually one of the major concerns. We propose a memory based recursive FFT design in FPGA for the low power base-band OFDM transmitter and receiver for WiMax (wireless metropolitan area network) application. It is implemented by radix-8 FFT. As results, the power consumption will be reduced by 28% compared to radix-4 FFT. The proposed architecture has three advantages: (1) fewer butterfly iterations to reduce power consumption, (2) pipeline of radix-8 butterfly to speed up clock frequency, (3) even distribution of memory access to make the best utilization efficiency of SRAM ports