Design of FPGA Based Instruction Fetch & Decode Module of 32-bit RISC (MIPS) Processor

In this paper, we analyze MIPS instruction format instruction data path decoder module function and design theory based on RISC CPU instruction set. Furthermore, we design instruction fetch (IF) module of 32-bit CPU based on RISC CPU instruction set. Function of IF module mainly includes fetch instruction and latch module address arithmetic module check validity of instruction module synchronous control module. Through analysis of function and theory of RISC CPU instruction decoder module, we design instruction decoder (ID) module of 32-bit CPU by pipeline theory. The instruction decoder includes register file, write back data to register file, sign bit extend, relativity check, and it is simulated on QuartusII successfully. Static time sequence shows the instruction fetch & decode module completing required function.