Comparision of Hierarchial Mixed-Size Placement Algorithms for VLSI Physical Synthesis

Placement is a physical synthesis task that transforms a block/gate/transistor-level net list into an actual layout for timing convergence. It is a crucial step that assembles the basic building blocks of logic net list and establishes the overall timing characteristic of a design by determining exact locations of circuit elements within a given region. If a design is placed poorly, it is virtually impossible to close timing, no matter how much other physical synthesis and routing optimizations are applied to it. The algorithms for solving the mixed size placement problem fall into two categories, flat and hierarchical. The strategy of flat algorithm is to view both standard cells and macro blocks as the same placement components, whose advantage is that low complexity placement algorithm, such as quadratic-based algorithm, can be used to do the placement with very high speed. The strategy of hierarchical algorithm is to do the placement through block level and cell level, and the overlaps involving macro blocks are eliminated in block level. In both levels, the number of placement components reduces considerably.