Design and Implementation of High Performance AHB Reconfigurable Arbiter for Onchip Bus Architecture

Resolution is a big issue in SOC (system On Chip) while dealing with number of master trying to sense a single data bus. The effectiveness of a system to resolve this priority resides in its ability to logical assignment of the chance to transmit data width of the data, response to the interrupts etc. The purpose of this paper is to propose the scheme to implement reconfigurable architecture so that it can be interface with any common IP core of such a system using the specification of AMBA bus protocol. The scheme involves the typical AMBA features of ´single clock edge transition´, Split transaction´, ´several bus masters´, ´burst transfer´. The bus arbiter ensures that only one bus master at a time is allowed to initiate data transfers. Here we have proposed and implemented the reconfigurable arbitration algorithm, such as highest priority or fair access and round robin can be implemented depending on the application requirements. The design architecture is written using VHDL(Very High Speed Integrated Circuits Hardware Description Language) code using Xilinx ISE Tools. The architecture is modeled and synthesized using RTL(Register Transfer Level) abstraction and Implemented on Virtex2 series.