VHDL Environment for Floating Point Arithmetic Logic Unit-ALU Design and Simulation

VHDL environment for floating point arithmetic and logic unit design using pipelining is introduced; the novelty in the ALU design with pipelining provides a high performance ALU to execute multiple instructions simultaneously. In top-down design approach, four arithmetic modules, addition, subtraction, multiplication and division are combined to form a floating point ALU unit. Each module is divided into sub- modules with two selection bits are combined to select a particular operation. Each module is independent to each other. The modules are realized and validated using VHDL simulation in the Xilinx12.1i software.