Modeling of Sigma-Delta Modulator Non-Idealities in MATLAB/SIMULINK

Switched capacitor (SC) modulator performance is prone to various nonidealities, especially at integrator stage, which affects overall circuit performance. In this paper a set of models are proposed which takes into account SC sigma-delta (ΣΔ) modulator nonidealities, such as sampling jitter since switching circuitry is included, kT/C noise, and operational amplifier parameters (noise, finite dc gain, finite bandwidth, slew-rate and saturation voltages). Each nonidealities are modelled mathematically and their behaviour is verified using different analysis in MATLAB Simulink. Description of the considered effect described herewith simulation results and implementative details. Simulation results on a second-order SC ΣΔ modulator demonstrate the validity of the models proposed.