DocumentCode :
2484357
Title :
Backlog Analysis of Maximal Matching Switching with Speedup
Author :
Cogill, Randy ; Lall, Sanjay
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA
fYear :
2006
fDate :
13-15 Dec. 2006
Firstpage :
1876
Lastpage :
1881
Abstract :
In this paper we analyze the average backlog in a combined input-output queued switch using a maximal size matching scheduling algorithm. We compare this average backlog to the average backlog achieved by an optimal switch. We model the cell arrival process as independent and identically distributed between time slots and uniformly distributed among input and output ports. For switches with many input and output ports, the backlog associated with maximal size matching with speedup 3 is no more than 3 1/3 times the backlog associated with an optimal switch. Moreover, this performance ratio rapidly approaches 2 as speedup increases
Keywords :
optimisation; queueing theory; scheduling; telecommunication switching; backlog analysis; cell arrival process; input-output queued switch; maximal matching switching algorithm; optimal switch; speedup; Algorithm design and analysis; Computational efficiency; Impedance matching; Processor scheduling; Queueing analysis; Switches; Throughput; Traffic control; USA Councils; Upper bound;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Decision and Control, 2006 45th IEEE Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
1-4244-0171-2
Type :
conf
DOI :
10.1109/CDC.2006.377265
Filename :
4178060
Link To Document :
بازگشت