Title :
The world´s fastest CPU and SMP node: Some performance results from the NEC SX-9
Author :
Zeiser, Thomas ; Hager, Georg ; Wellein, Gerhard
Author_Institution :
Erlangen Regional Comput. Center, Univ. of Erlangen-Nuremberg, Erlangen, Germany
Abstract :
Classic vector systems have all but vanished from recent TOP500 lists. Looking at the newly introduced NEC SX-9 series, we benchmark its memory subsystem using the low level vector triad and employ an advanced lattice Boltzmann flow solver kernel to demonstrate that classic vectors still combine excellent performance with a well-established optimization approach. Results for commodity x86-based systems are provided for reference.
Keywords :
memory architecture; parallel machines; CPU; NEC SX-9; SMP node; lattice Boltzmann flow solver kernel; memory subsystem; optimization; vector architecture; x86-based system; Arithmetic; Bandwidth; CMOS technology; Computer buffers; Kernel; Lattice Boltzmann methods; National electric code; Registers; SDRAM; Supercomputers;
Conference_Titel :
Parallel & Distributed Processing, 2009. IPDPS 2009. IEEE International Symposium on
Conference_Location :
Rome
Print_ISBN :
978-1-4244-3751-1
Electronic_ISBN :
1530-2075
DOI :
10.1109/IPDPS.2009.5161089
