Optimization of parallel task execution on the adaptive reconfigurable group organized computing system

Author

Kirischian, Lev

Author_Institution

Dept. of Electr. & Comput. Eng., Ryerson Polytech. Inst., Toronto, Ont., Canada

fYear

2000

fDate

2000

Firstpage

100

Lastpage

105

Abstract

This paper presents the architecture organization of a task adaptive reconfigurable high-performance computing system for parallel processing of data-flow tasks. The architecture of this reconfigurable system allows flexible distribution of uniform configurable resources (FPGA-based) between tasks. Each task corresponds to a specific group processor (GP) adapted for the task requirements. The paper discusses the method of selecting the optimal group processor configuration and mapping group processors on the field of configurable resources. The performance results of the first prototype of the ARGO-parallel computing system are presented

Keywords

data flow computing; field programmable gate arrays; optimisation; parallel architectures; parallel machines; performance evaluation; reconfigurable architectures; ARGO; FPGA; adaptive reconfigurable group organized computing; data-flow tasks; high-performance computing system; optimal group processor configuration; parallel architecture; parallel computing system; parallel processing; parallel task execution optimization; task adaptive reconfigurable system; uniform configurable resources; Computer architecture; Concurrent computing; Digital signal processing; Electronic mail; Field programmable gate arrays; Hardware; Parallel processing; Process control; Prototypes; Reconfigurable architectures;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Computing in Electrical Engineering, 2000. PARELEC 2000. Proceedings. International Conference on

Conference_Location

Trois-Rivieres, Que.

Print_ISBN

0-7695-0759-X

Type

conf

DOI

10.1109/PCEE.2000.873610

Filename

873610