Thyristor Gate Control implementation on FPGA for particle accelerator facilities

This paper provides the general description, design guidelines and implementation issues of a digital Thyristor Gate Control (TGC) system developed for particle accelerator facilities. The present proposal improves the TGC performance by replacing the conventional synchronization method based on a single phase zero crossing Phase Lock Loop (PLL) with a novel three-phase synchronous method known as Variable Sampling Period Filter PLL (VSPF-PLL). The proposal is implemented in a custom board and it is tested in a 6-phase power converter under a very distorted mains.