Title :
Optimal partitioning for FPGA based regular array implementations
Author :
Derrien, S. ; Rajopadhye, S. ; Sur-Kolay, S.
Author_Institution :
IRISA, Rennes, France
Abstract :
Reconfigurable Accelerators (RAs) have the potential to provide significant speed-up over many traditional software implementations. However, their effective performance is often limited by their input/output (IO) capabilities rather than by their computational power. Hence it important to take these constraints into consideration when implementing an algorithm on such an architecture. We propose an IO conscious optimal partitioning strategy for RA based regular array implementations
Keywords :
field programmable gate arrays; logic partitioning; parallel architectures; reconfigurable architectures; systolic arrays; FPGA based regular array implementations; RA based regular array implementations; input/output capabilities; loop parallelisation; optimal partitioning; reconfigurable accelerators; Analytical models; Bandwidth; Clocks; Communication system control; Field programmable gate arrays; Intersymbol interference; Parallel processing; Performance analysis; Registers; Systolic arrays;
Conference_Titel :
Parallel Computing in Electrical Engineering, 2000. PARELEC 2000. Proceedings. International Conference on
Conference_Location :
Trois-Rivieres, Que.
Print_ISBN :
0-7695-0759-X
DOI :
10.1109/PCEE.2000.873620
