Title :
Virtual time window for balancing progress on parallel optimistic protocol and its effect on computation granularity
Author_Institution :
Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, USA
Abstract :
Scheduling events on parallel discrete event simulation (PDES) affects the performance of parallel optimistic simulation significantly. As an event scheduling scheme, the virtual time window (VTW) protocol is applied. The virtual time window has influences not only on balancing the progress of logical processes, but also on adjusting the computation granularity between two consecutive interprocessor communications. The author investigates various performance aspects of the virtual time window protocol for parallel optimistic logic circuit simulation on a cluster of SUN Ultra workstations interconnected by a 100 Mbps Ethernet. With the goal of designing an adaptive optimistic synchronization protocol, the author measures and interprets the influence of the control parameter, i.e., the size of time window, on the various aspects of the simulation state, such as rollback and communication costs, which are related to the dynamic state of parallel logic circuit simulation. In addition, execution activity and simulation progress are considered
Keywords :
circuit analysis computing; local area networks; logic circuits; parallel processing; processor scheduling; software performance evaluation; synchronisation; time warp simulation; 100 Mbit/s; Ethernet; SUN Ultra workstation cluster; adaptive optimistic synchronization protocol; communication costs; computation granularity; consecutive interprocessor communications; control parameter; dynamic state; event scheduling; execution activity; logical processes; parallel discrete event simulation; parallel optimistic logic circuit simulation; parallel optimistic protocol; parallel optimistic simulation; progress balancing; rollback; virtual time window protocol; Circuit simulation; Computational modeling; Discrete event simulation; Ethernet networks; Integrated circuit interconnections; Logic circuits; Processor scheduling; Protocols; Sun; Workstations;
Conference_Titel :
Simulation Symposium, 1998. Proceedings. 31st Annual
Conference_Location :
Boston, MA
Print_ISBN :
0-8186-8418-6
DOI :
10.1109/SIMSYM.1998.668415