Low-power turbo equalizer architecture

Author

Lee, Seok Jun ; Shanbhag, R Naresh ; Singer, C Andrew

Author_Institution

ECE Dept., Illinois Univ., Urbana, IL, USA

fYear

2002

fDate

16-18 Oct. 2002

Firstpage

33

Lastpage

38

Abstract

In this paper, we propose a low complexity architecture for turbo equalizers. Turbo equalizers jointly equalize and decode the received signal by exchanging soft information iteratively. The proposed architecture employs early termination of the iterative process when it does not impact the bit-error rate (BER). Early termination enables the powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that the complexity is reduced by 20% ∼ 59% and 8% ∼ 58% in equalization and decoding, respectively. In addition, the number of iterations is reduced by 30% ∼ 47% with negligible degradation in BER.

Keywords

circuit complexity; decoding; equalisers; error statistics; turbo codes; BER; bit-error rate; decoder; early iterative process termination; low complexity architecture; low-power turbo equalizer architecture; soft-input soft-output equalizer; Binary phase shift keying; Bit error rate; DSL; Decision feedback equalizers; Degradation; Design optimization; Frequency; Intersymbol interference; Iterative decoding; Termination of employment;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on

ISSN

1520-6130

Print_ISBN

0-7803-7587-4

Type

conf

DOI

10.1109/SIPS.2002.1049681

Filename

1049681