Title :
Low error fixed-width modified Booth multiplier
Author :
Cho, K.J. ; Lee, K.C. ; Chung, J.G. ; Parhi, K.K.
Author_Institution :
Dept. of Electron. & Inf. Eng., Chonbuk Nat. Univ., South Korea
Abstract :
This paper presents an error compensation method for a modified Booth fixed-width multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50% by the proposed error compensation method compared with the existing method with slight increase in the overhead of bias generation circuit.
Keywords :
digital arithmetic; error compensation; logic circuits; multiplying circuits; quantisation (signal); bias generation circuit; error compensation method; fixed-width modified Booth multiplier; low error Booth multiplier; quantization error; Adders; Circuit simulation; Digital signal processing; Error compensation; Finite wordlength effects; Linear regression; Quantization; Signal generators; Statistical analysis; USA Councils;
Conference_Titel :
Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on
Print_ISBN :
0-7803-7587-4
DOI :
10.1109/SIPS.2002.1049683