An assessment of VLSI and embedded software implementations for Reed-Solomon decoders

Author

Fill, Ted S. ; Gulak, P. Glenn

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

fYear

2002

fDate

16-18 Oct. 2002

Firstpage

99

Lastpage

102

Abstract

This paper examines Reed-Solomon time-domain and frequency-domain decoder implementations in both software and hardware. The focus was on designing area-efficient, low-power and low-complexity decoders suitable for today´s moderate data-rate applications. Two decoder chips were designed using a synthesized standard cell library in a 0.18 μm CMOS process, targeting a 160 Mbps decoding rate. The time-domain decoder was fabricated with a core area of 1.50 mm².

Keywords

CMOS digital integrated circuits; Reed-Solomon codes; VLSI; decoding; frequency-domain analysis; low-power electronics; time-domain analysis; 0.18 micron; 160 Mbit/s; CMOS; Reed-Solomon decoders; VLSI; area-efficient decoders; decoding rate; embedded software implementations; frequency-domain decoder; low-complexity decoders; low-power decoders; standard cell library; time-domain decoder; DSL; Decoding; Digital video broadcasting; Embedded software; Error correction; Error correction codes; Hardware; Reed-Solomon codes; Time domain analysis; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on

ISSN

1520-6130

Print_ISBN

0-7803-7587-4

Type

conf

DOI

10.1109/SIPS.2002.1049692

Filename

1049692