Design of DSP instructions and their hardware architecture for a Reed-Solomon codec

This paper presents new DSP (digital signal processor) instructions and their hardware architecture to implement efficiently RS (Reed-Solomon) encoding and decoding, which is one of the most widely used FEC (Forward Error Control) algorithms. The proposed DSP architecture can implement various programmable primitive polynomials, and thus, hardwired RS codecs can be replaced. The new instructions and their hardware architecture perform GF (Galois field) operations using the proposed GF multiplier and adder. Therefore, the proposed DSP architecture can significantly reduce the number of clock cycles compared with existing DSP chips. It can perform RS decoding at a rate of up to 175.5 Mbps on 100 MHz DSP chips.