Parameterized model order reduction with guaranteed passivity for PEEC Circuit analysis

We present a novel parameterized model order reduction technique applicable to the Partial Element Equivalent Circuit analysis that provides parametric reduced order models, stable and passive by construction, over a user defined design space. We treat the construction of parametric reduced order models on scattered design space grids. This new parameterized model order reduction technique is based on the hybridization of traditional passivity-preserving model order reduction methods and interpolation schemes based on a class of positive interpolation operators, in order to guarantee overall stability and passivity of the parametric reduced order model. Pertinent numerical examples validate the proposed approach.