Parasitic resistance extraction errors with implications for FET model accuracy around V/sub ds/=0

The accuracy of non-linear FET models around the origin in the V/sub gs/-V/sub ds/ bias plane, may be seriously affected by errors in the extracted values of the source and drain parasitic resistances. In this paper we present test results that prove how relatively small errors of this kind, which can be easily encountered when using conventional extraction techniques, can lead to large errors in the values extracted for some intrinsic parameters, and in particular for the two gate capacitances. The source of these errors is investigated and, as a solution, an improved extraction methodology is offered, which substantially reduces the risk of such errors.