High sampling rate retimed DLMS filter implementations in Virtex-II FPGA

A pipelined architecture aids the efficient implementation of a Delayed LMS algorithm but requires a considerable processing delay. In this paper, an efficient method for determining the delays in the feedback loop of a DLMS filter is presented. This is used to design a series of Retimed Delayed LMS (RDLMS) architectures which allow a higher throughput rate and 66.7% reduction in the delays of previous designs. The resulting design also converges 5 times faster. Three architectures and three hardware shared versions have been designed and implemented using the Virtex-II FPGA. A speed of 182 Megasamples/s has been achieved.