High sampling rate retimed DLMS filter implementations in Virtex-II FPGA

Author

Yi, Y. ; Woods, R. ; Ting, L.K. ; Cowna, C.F.N.

Author_Institution

Sch. of Electr. & Electron. Eng., Queen´´s Univ., Belfast, UK

fYear

2002

fDate

16-18 Oct. 2002

Firstpage

139

Lastpage

145

Abstract

A pipelined architecture aids the efficient implementation of a Delayed LMS algorithm but requires a considerable processing delay. In this paper, an efficient method for determining the delays in the feedback loop of a DLMS filter is presented. This is used to design a series of Retimed Delayed LMS (RDLMS) architectures which allow a higher throughput rate and 66.7% reduction in the delays of previous designs. The resulting design also converges 5 times faster. Three architectures and three hardware shared versions have been designed and implemented using the Virtex-II FPGA. A speed of 182 Megasamples/s has been achieved.

Keywords

VLSI; circuit feedback; convergence of numerical methods; digital filters; field programmable gate arrays; least mean squares methods; pipeline processing; timing; VLSI; Virtex-II FPGA; delayed LMS algorithm; feedback loop; high sampling rate filter; pipelined architecture; retimed DLMS filter implementations; retimed delayed LMS architectures; Circuits; Computer architecture; Delay; Error correction; Feedback loop; Field programmable gate arrays; Finite impulse response filter; Least squares approximation; Pipeline processing; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on

ISSN

1520-6130

Print_ISBN

0-7803-7587-4

Type

conf

DOI

10.1109/SIPS.2002.1049699

Filename

1049699