Implementation of high throughput soft output Viterbi decoders

Author

Yeo, Engling ; Augsburger, Stephanie ; Davis, Wm Rhett ; Nikolic, Borivoje

Author_Institution

California Univ., Berkeley, CA, USA

fYear

2002

fDate

16-18 Oct. 2002

Firstpage

146

Lastpage

151

Abstract

The architectural considerations for VLSI implementations of soft output Viterbi decoders are presented. Structural transformation of the add-compare-select structures provides high throughput with small area overhead. Modifications to the survivor memory unit and a comparison between the register exchange and memory traceback methods are highlighted. A 4 mm² demonstration chip, consisting of two parallel, 8-state, 7-bit soft output Viterbi decoders, has been implemented in 0.18 μm CMOS technology, and decodes at 500 Mb/s with 1.8 V supply. These decoders are used with turbo codes, which have been demonstrated to achieve information rates close to the Shannon limit.

Keywords

CMOS digital integrated circuits; VLSI; Viterbi decoding; digital signal processing chips; parallel architectures; turbo codes; 0.18 micron; 1.8 V; 500 Mbit/s; 7 bit; CMOS technology; SOVA decoder; VLSI implementations; add-compare-select structures; high throughput Viterbi decoders; memory traceback method; register exchange method; soft output Viterbi algorithm; soft output Viterbi decoders; survivor memory unit; turbo codes; CMOS technology; Convolutional codes; Information rates; Iterative decoding; Magnetic recording; Registers; Throughput; Turbo codes; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on

ISSN

1520-6130

Print_ISBN

0-7803-7587-4

Type

conf

DOI

10.1109/SIPS.2002.1049700

Filename

1049700