Flexible implementation of a WCDMA Rake receiver

Author

Harju, Lusse ; Kuulusa, Mika ; Nurmi, Jari

Author_Institution

Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland

fYear

2002

fDate

16-18 Oct. 2002

Firstpage

177

Lastpage

182

Abstract

This paper presents an ASIC implementation of a WCDMA Rake receiver. The implementation is based on a FlexRake architecture that shares resources between multipath components and uses parallelism for multiple code channels. This approach facilitates the multipath allocation and improves the receiver modularity. The architecture was implemented using register-transfer-level VHDL description and logic synthesis with standard cells. Synthesis for 0.35 μm technology resulted in 0.894 mm² area and 3.63 mW power consumption at 2.7 V.

Keywords

CMOS digital integrated circuits; application specific integrated circuits; code division multiple access; digital signal processing chips; diversity reception; multipath channels; quadrature phase shift keying; radio receivers; telecommunication computing; 0.35 micron; 2.7 V; 3.63 mW; ASIC implementation; FlexRake architecture; QPSK modulation; RTL VHDL description; W-CDMA Rake receiver; flexible implementation; logic synthesis; multipath allocation; multipath components; multiple code channels; parallelism; receiver modularity; register-transfer-level description; resources sharing; standard cells; wideband CDMA; Application specific integrated circuits; Computer architecture; Delay estimation; Diversity reception; Fading; Fingers; Gold; Multiaccess communication; Multipath channels; RAKE receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on

ISSN

1520-6130

Print_ISBN

0-7803-7587-4

Type

conf

DOI

10.1109/SIPS.2002.1049705

Filename

1049705