DocumentCode :
2487140
Title :
Analysis of coupling-induced jitter in FPGA transceiver
Author :
Chand, Kundan ; Liu, Geping ; Chow, Daniel
Author_Institution :
Altera Corp., San Jose, CA, USA
fYear :
2010
fDate :
25-30 July 2010
Firstpage :
573
Lastpage :
578
Abstract :
This paper analyses jitter increase mechanism due to parallel IO simultaneous switching noise (SSN), while FPGA transceiver operates at multi-gigabit data rates or higher. Several jitter measurement methods and relevant simulations are used to diagnose noise sources and coupling paths. This paper illustrates that transmitter jitter profile is related to power supply noise and inductive crosstalk characteristics. These findings helped improve PDN design resulting in better device jitter performance.
Keywords :
circuit noise; coupled circuits; crosstalk; field programmable gate arrays; jitter; power supply circuits; transceivers; FPGA transceiver; PDN design; SSN; coupling paths; coupling-induced jitter; device jitter performance; inductive crosstalk characteristics; jitter increase mechanism; jitter measurement methods; multigigabit data rates; noise sources diagnosis; parallel IO simultaneous switching noise; power supply noise; relevant simulations; transmitter jitter profile; Couplings; Impedance; Jitter; Noise; Pins; Resonant frequency; Transceivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electromagnetic Compatibility (EMC), 2010 IEEE International Symposium on
Conference_Location :
Fort Lauderdale, FL
ISSN :
2158-110X
Print_ISBN :
978-1-4244-6305-3
Type :
conf
DOI :
10.1109/ISEMC.2010.5711340
Filename :
5711340
Link To Document :
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