High-level synthesis with coarse grain reconfigurable components

High-level synthesis is the process of balancing the distribution of RTL components throughout the execution of applications. However, a lot of balancing and optimization opportunities exist below RTL. In this paper, a coarse grain reconfigurable RTL component that combines a multiplier and a number of additions is presented and involved in high-level synthesis. The gate-level synthesis methodology for this component imposes practically no extra hardware than a normal multiplier while involvement in high-level synthesis is performed with a scheduling postprocessor. Following this approach, components that would remain idle in certain control steps are working full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application. The results obtained with different DSP benchmarks show a maximum performance gain of almost 70% with a 45% datapath area gain.