Microprocessor cores

Author

Burdass, Andrew ; Campbell, Gary ; Grisenthwaite, Richard ; Gwilt, David ; Harrod, Peter ; York, Richard

Author_Institution

ARM Ltd., Cambridge, UK

fYear

2000

fDate

2000

Firstpage

17

Lastpage

22

Abstract

This paper compares and contrast two very different approaches to testing cached CPU macrocells that are typically embedded in a System on Chip (SoC). One uses a test bus to apply functional vectors, while the other uses a combination of scan insertion, memory BIST and test collars. IP protection issues and nonintrusive tracing are also discussed

Keywords

automatic test pattern generation; boundary scan testing; built-in self test; cellular arrays; embedded systems; hardware-software codesign; industrial property; logic testing; microprocessor chips; INTEST wrapper; IP protection issues; cached CPU macrocells; debugging; embedded in SoC; fault coverage; full custom processor core; functional vector; macrocell cores; memory BIST; microprocessor cores; nonintrusive tracing; scan insertion; synthesisable core test; test bus; test collars; Automatic test pattern generation; Built-in self-test; Databases; Embedded system; Logic testing; Macrocell networks; Microprocessors; Protection; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Workshop, 2000. Proceedings. IEEE European

Conference_Location

Cascais

ISSN

1530-1877

Print_ISBN

0-7695-0701-8

Type

conf

DOI

10.1109/ETW.2000.873774

Filename

873774