Static and dynamic on-chip test response evaluation using a two-mode comparator

Author

De Venuto, D. ; Ohletz, M.J. ; Matarrese, G.

Author_Institution

Dip. di Elettrotecnica ed Elettronica, Politecnico di Bari, Italy

fYear

2000

fDate

2000

Firstpage

47

Lastpage

52

Abstract

A design-for-testability implementation to achieve high fault coverages in the analogue functional blocks of mixed circuit ASICs is presented in this feasibility study. To this end existing op amps or OTAs are converted into clocked comparators with hysteresis and variable reference levels. The resulting two-mode comparators are connected to specific internal nodes. Depending on the mode this node can be either statically and/or dynamically evaluated on-chip without the need to bring an analogue signal off-chip. Results from first simulations and measurements on a test circuit realised in 0.35 μm technology are presented

Keywords

boundary scan testing; comparators (circuits); design for testability; integrated circuit testing; mixed analogue-digital integrated circuits; operational amplifiers; OTA; analogue functional blocks; boundary scan; clocked comparators; design-for-testability implementation; dynamic on-chip test response; functional conversion; high fault coverage; hysteresis; mixed circuit ASIC; op amps; specific internal nodes; static on-chip test response; two-mode comparators; variable reference levels; Circuit faults; Circuit simulation; Circuit testing; Clocks; Hysteresis; Integrated circuit measurements; Integrated circuit technology; Latches; Microelectronics; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Workshop, 2000. Proceedings. IEEE European

Conference_Location

Cascais

ISSN

1530-1877

Print_ISBN

0-7695-0701-8

Type

conf

DOI

10.1109/ETW.2000.873778

Filename

873778