Title :
A parameterizable fault simulator for bridging faults
Author :
Engelke, Piet ; Becker, Bernd ; Keim, Martin
Author_Institution :
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
Abstract :
We present the concept of a multiple-valued logic simulator that is able to more accurately determine the possible behavior of a circuit in the presence of bridging faults. By a user defined mapping of a range of voltages to a logic value the simulator takes care of certain voltages more closely than common bridge fault simulators that map all voltages to either logic 1 or 0. Experimental results are given to demonstrate the improved fault detection possibilities
Keywords :
CMOS logic circuits; fault simulation; integrated circuit testing; logic simulation; logic testing; multivalued logic circuits; bridging faults; improved fault detection; multiple-valued logic simulator; parameterizable fault simulator; range of voltages; user defined mapping; voltage-logic mapping; Bridge circuits; CMOS logic circuits; Circuit faults; Circuit simulation; Computational modeling; Delay; Semiconductor device modeling; Switches; Threshold voltage; Voting;
Conference_Titel :
Test Workshop, 2000. Proceedings. IEEE European
Conference_Location :
Cascais
Print_ISBN :
0-7695-0701-8
DOI :
10.1109/ETW.2000.873780
