RTL-based functional test generation for high defects coverage in digital SOCs

Functional test is long viewed as unfitted for production test. The purpose of this contribution is to propose a RTL-based test generation methodology which can be rewardingly used both for design validation and to enhance the test effectiveness of classic, gate-level test generation. Hence, a RTL-based defect-oriented test generation methodology is proposed, for which a high defects coverage (DC) and a relatively short test sequence can be derived, thus allowing low-energy operation in test mode. The test effectiveness, regarding DC, is shown to be weakly dependent on the structural implementation of the behavioral description. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and the CMUDSP ITC´99 benchmark circuit