• DocumentCode
    2488259
  • Title

    Circuit partitioning under capacity and I/O constraints

  • Author

    Shih, Minshine ; Kuh, Emest S.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    1994
  • fDate
    1-4 May 1994
  • Firstpage
    659
  • Lastpage
    662
  • Abstract
    This paper proposes an effective method for solving multi-way circuit partitioning problems under capacity (size) and I/O pin count constraints. The objective is the total net cuts among partitions. We first linearize the quadratic objective function into a linear function, then we assign circuit components sequentially according to this linear function while avoiding capacity or I/O violations. The resulting assignment (partitioning) is used to compute another linear cost function and the sequential assignment is repeated. This process can be iterated for a fix number of times to get a good final solution. Experimental results for several benchmark circuits are also given to demonstrate its effectiveness
  • Keywords
    circuit layout CAD; integrated circuit layout; iterative methods; I/O constraint; capacity constraint; linear function; multiway circuit partitioning problems; quadratic objective function; size constraint; Circuits; Cost function; Field programmable gate arrays; Hardware; Large-scale systems; Partitioning algorithms; Runtime; System performance; Temperature; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-1886-2
  • Type

    conf

  • DOI
    10.1109/CICC.1994.379637
  • Filename
    379637