Low cost concurrent test implementation for linear digital systems

Author

Bayraktaroglu, Ismet ; Orailoglu, Alex

Author_Institution

Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA

fYear

2000

fDate

2000

Firstpage

140

Lastpage

143

Abstract

An implementation of a low-cost, time-extended invariant-based concurrent test scheme for linear digital systems is presented. Both feedback and non-feedback systems are analyzed to identify gate and RT level implementation requirements for high on-line fault coverage. Simulation results on implementations satisfying the outlined requirements indicate that low latency, 100% on-line fault coverage is attained within hardware costs comparable to those of scan insertion

Keywords

FIR filters; IIR filters; adders; digital filters; error detection; fault simulation; logic testing; roundoff errors; FIR systems; IIR systems; RT level implementation requirements; VLSI; concurrent error detection; cyclic systems; fault masking; fault simulation; feedback systems; gate level implementation requirements; high on-line fault coverage; impulse response; linear digital systems; low cost concurrent test implementation; low latency; non-feedback systems; ripple-carry adder; round-off behaviour; time-extended invariant-based scheme; Circuit faults; Circuit simulation; Computer science; Costs; Delay; Digital systems; Fault detection; Hardware; Signal processing algorithms; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Workshop, 2000. Proceedings. IEEE European

Conference_Location

Cascais

ISSN

1530-1877

Print_ISBN

0-7695-0701-8

Type

conf

DOI

10.1109/ETW.2000.873791

Filename

873791