An efficient self-timed queue architecture for ATM switch LSI´s

A new approach to implement queues for controlling ATM switch LSI is presented. We combined a self-timed FIFO with a search circuit that finds the earliest entry for each output port. Using this architecture, queues provided for each output port can be effectively realized by a single FIFO. The delay priority and multicasting are supported without doubling the number of the queues. This new FIFO can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-μm CMOS process technology. Interstage transfer speed over 500 MHz and cycle time over 125 MHz were obtained