Title :
CA-CSTP: a new BIST architecture for sequential circuits
Author :
Corno, F. ; Reorda, M. Sonza ; Squillero, G. ; Violante, M.
Author_Institution :
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
Abstract :
Circular Self-Test Path (CSTP) is an attractive technique for implementing BIST in sequential circuits; unfortunately, there are cases in which the fault coverage it attains is unacceptably low. This paper proposes a new architecture, named CA-CSTP, which overcomes these limitations and always reaches a high fault coverage by exploiting a slightly more complex chain cell based on a Cellular Automata architecture. Experimental results show the effectiveness of our proposal
Keywords :
built-in self test; design for testability; logic CAD; sequential circuits; BIST architecture; CA-CSTP; cellular automata architecture; circular Self-Test Path; fault coverage; rule selection; sequential circuits; Application specific integrated circuits; Built-in self-test; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Process design; Proposals; Sequential circuits; World Wide Web;
Conference_Titel :
Test Workshop, 2000. Proceedings. IEEE European
Conference_Location :
Cascais
Print_ISBN :
0-7695-0701-8
DOI :
10.1109/ETW.2000.873795
