Composing specifications in VSPEC

As systems become increasingly complex and existing methodologies become insufficient to handle the complexity, the design community is beginning to look at formal methods for a possible solution. Techniques involving a limited use of formal techniques (such as semi-formal methods and equivalence checking) have given a glimpse of what full usage of formal techniques can achieve. For the use of formal methods to be a widely accepted methodology among designers, it must provide the designers with the capabilities of structuring specifications in a manner similar to the structuring they are used to using with programming languages. In this paper, we provide a description of the structuring capabilities of VSPEC (VHDL SPECification), a requirements specification language for VHDL. These capabilities include the use of multiple pre- and post-condition pairs within a single specification and combination of specifications using common Boolean operators