Lean integration: achieving a quantum leap in performance and cost of logic LSIs

Lean integration aims at a fundamental change in top-down design by following the path from CISC to RISC. The central idea is a lean cell, which has a tree-shaped nMOS network with input ports placed at the end of an every branch of the tree. A lean cell has flexibility of transistor-level circuit design and full compatibility with conventional cell-based design. An extremely simple lean-cell library with only 7 cells and a synthesis tool called “Circuit Inventor”, which uses the lean cells, are developed and they are compared with the conventional “complex” CMOS library that has over 60 cells. The results show that the area, the delay, and the power dissipation are improved by lean integration and performance cost ratio is improved by a factor of three