Hybrid Test Data Compression Technique for Low-Power Scan Test Data

The large test data volume and power consumption are major problems in testing system-on-a-chip (SoC) which is a key component of today´s embedded system. To reduce the test application time from an automatic test equipment (ATE), a new test data compression technique is proposed in this paper. Don´t-cares in a pre-computed test cube set are assigned to reduce the test power consumption. Then, fully specified low-power test data is transformed to improve compression efficiency by neighboring bit-wise exclusive-or technique. Finally, test set converted is compressed to reduce test application time.