PLL timing design techniques for large-scale, high-speed, low-power, and low-cost SRAMs

Author

Nakamura, Kazuyulu ; Kuhara, Sigeru ; Kimura, Tohru ; Takada, Masahide ; Suzuki, Hisamitsu ; Yoshida, Hiroshi ; Yamazaki, Tohru

Author_Institution

NEC Corp., Kawasaki, Japan

fYear

1994

fDate

1-4 May 1994

Firstpage

559

Lastpage

562

Abstract

PLL timing design techniques introduced here feature (1) a word-line resetting-equalization scheme employing a clock-cycle proportional pulse, (2) a clock cyclic input buffer power-cutting scheme employing a clock-edge lookahead pulse, and (3) a super-pipelined parallel test scheme which allows the evaluation of high-speed LSIs by low-speed LSI testers. These techniques successfully contribute to the development of a 7 ns 16 Mb BiCMOS SRAM LSI

Keywords

BiCMOS memory circuits; SRAM chips; automatic testing; buffer circuits; clocks; digital phase locked loops; integrated circuit testing; large scale integration; timing; 16 Mbit; 7 ns; BiCMOS; PLL timing design techniques; SRAMs; clock-cycle proportional pulse; clock-edge lookahead pulse; high-speed LSIs; input buffer; low-speed LSI testers; power-cutting scheme; super-pipelined parallel test scheme; word-line resetting-equalization scheme; Circuit testing; Clocks; Large scale integration; Large-scale systems; Phase locked loops; Pulse generation; Random access memory; Ring oscillators; Timing; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379660

Filename

379660