Imposing tight specifications on analog IC´s through simultaneous placement and module optimization

Techniques are presented for simultaneous placement and module optimization for analog ICs. An algorithmic approach to module generation provides alternative sets of modules, optimized with respect to performance but with different trade-offs among area, parasitics and matching. A simulated annealing algorithm performs the placement, selecting among the available configurations the one that best fulfils all performance and geometric requirements. Compared to standard approaches, the flexibility of placement is considerably increased, thus allowing the enforcement of tighter specifications